1. Field of the Invention
The present invention relates to a simulator for verifying signal waveforms between electronic components mounted on a printed-circuit board. The invention more particularly relates to a simulator taking account of timing in an electronic component and signal transmission through transmission lines on a printed-circuit board.
2. Description of the Background Art
As the processing speed of an electronic component increases, timing simulation within the electronic component as well as transmission line simulation for wiring on a printed-circuit board become necessary in order to preliminarily detect any deficiency in circuits within the electronic component and that in a wiring pattern of the printed-circuit board.
FIG. 1 is a block diagram schematically illustrating a structure of a conventional timing simulator. The timing simulator includes a hardware description language holding section 101 provided with a logic circuit having its operation described with the hardware description language, a test pattern holding section 102 where a test pattern to be input to the logic circuit is stored, a timing simulation section 103 simulating the timing of the logic circuit by inputting the test pattern to the logic circuit having its operation described with the hardware description language, a timing simulation result holding section 104 holding result of the simulation executed by timing simulation section 103, and a timing simulation result display section 105 displaying the result of the timing simulation.
FIG. 2 is a block diagram schematically illustrating a structure of a conventional transmission line simulator. The transmission line simulator includes a circuit connecting information holding section 111 holding information on connection between electronic components mounted on a printed-circuit board, a wiring portion simulation model holding section 112 holding a simulation model of a wiring portion (transmission line) of the printed-circuit board, an I/O model holding section 113 holding a driver section and a receiver section of a modeled electronic component, a transmission line simulation section 114 simulating the transmission line using the circuit connecting information, the wiring portion simulation model, and the I/O model, a transmission line simulation result holding section 115 holding the result of the simulation by transmission line simulation section 114, a transmission delay information holding section 116 holding delay information of the transmission line determined by transmission line simulation section 114, and a transmission line simulation result display section 117 displaying the result of the transmission line simulation.
Transmission line simulation section 114 simulates the transmission line and stores the result of the transmission line simulation in transmission line simulation result holding section 115, and stores delay information with respect to the transmission line in transmission delay information holding section 116 in a form of SDF (Standard Delay Format) which can be used by the timing simulator.
When the entire printed-circuit board is simulated using the timing simulator and the transmission line simulator described above, timing simulation section 103 in the timing simulator uses the delay information stored in the SDF form in transmission delay information holding section 116 in the transmission line simulator to simulate circuits in an electronic component.
When the method is used of simulating the entire printed-circuit board using the timing simulator and the transmission line simulator described above, the result of the simulation presented to the user has the form which is supplied by the timing simulator. Therefore, the user can see the result only by logical values of a low level and a high level. Specifically, verification for signal integrity design taking account of reflection and ringing that are important factors for design of the printed-circuit board is difficult.